1. FIELD OF THE INVENTION
The present invention relates to a parallel processor apparatus for performing high speed digital processing on a video signal, etc.
2. DESCRIPTION OF THE RELATED ART
As an apparatus for performing digital processing at a high speed on a video signal of the digital format, for example, there is known the parallel processor apparatus disclosed in Childere, J. et al.,"SVP: SERIAL VIDEO PROCESSOR/Proceedings of the IEEE 1990 CUSTOM INTEGRATED CIRCUITS CONFERENCE, pp. 17.3.1 to 17.3.4".
Below, an explanation will be made of the apparatus (SVP processing apparatus) disclosed in the above-described document referring to FIG. 1 and FIG. 7.
First, the configuration of the structure of the parallel processor 8 will be explained referring to FIG. 1. FIG. 1 is a view of the configuration of a conventional parallel processor.
The parallel processor 8 is a parallel processor apparatus having m number of individual processors the 80.sub.1 to 80.sub.m and is configured so as to convert the, for example, the 8-bit word configuration data of pixels (pixel value D.sub.i, i=1, 2, . . . , m, the same in the explanation of the related art below) of the serially input video signal to parallel data for every horizontal period (one line's worth) by registers R1 to Rm, perform digital processing on these pixel values D.sub.i in the individual processors 80.sub.1 to 80.sub.m, convert the results Q.sub.i of the processing to serial data again by the registers R1 to Rm, and output the same from an output terminal OUTT.
The individual processors 80.sub.l to 80.sub.m are provided in the same number as the number m of pixels included in one line and corresponding to the pixels. Each is constituted by a register (Ri) 806.sub.i, registers (Rij) 808.sub.i, 810.sub.i, 812.sub.i, an individual delay element (Gi) 802.sub.i, an individual delay element (Hi) 804.sub.i, an arithmetic and logic unit (ALUi) 814.sub.i, a switch (Ui) 816.sub.i, switch (Si) 818.sub.i, switch (Vi) 826.sub.i, switch (Ti) 828.sub.i, switches (Sij) 820.sub.i, 822.sub.i, 824.sub.i, and switches (Tij) 840.sub.i, 842.sub.i and 844.sub.i (j=0, 1, 2, the same for the following).
The individual delay elements (Gi) 802.sub.i are serially connected. The individual delay elements (Gi) 802.sub.i give to the read pointer signal RP input from the input terminal PRT of the parallel processor 8 exactly a delay of a time corresponding to the time during which one pixel of the video signal is input.
The individual delay elements (Hi) 804.sub.i are serially connected. The individual delay elements (Hi) 804.sub.i give to the write pointer signal WP input from the input terminal PRT of the parallel processor 8 a delay time corresponding to one pixel of the video signal.
The registers (Ri) 806.sub.i are each a register having for example an 8-bit width, having an input terminal which is connected via a switch (Ui) 816.sub.i to the signal INT of the parallel processor 8 and via the switch (Ti) 818.sub.i to the write bit line WBi of the arithmetic and logic unit (ALUi) 814.sub.i, and having an output terminal which is connected via the switch (Vi) 826.sub.i to the output terminal OUTT of the parallel processor 8 and via the switch (Ti) 828.sub.i to the read bit line RBi of the arithmetic and logic unit (ALUi) 814.sub.i.
The register (Ri) 806.sub.i holds the pixel value D.sub.i input from the input terminal INT of the parallel processor 8 via the switch (Ui) 816.sub.i or the result of processing Q.sub.i input from the write bit line WBi of the arithmetic and logic unit (ALUi) 814.sub.i via the switch (Ti) 818.sub.i and outputs the held data via the switch (Vi) 826.sub.i to the output terminal OUTT of the parallel processor 8 or via the switch (Ti) 828.sub.i to the read bit line RBi of the arithmetic and logic unit (ALUi) 814.sub.i.
The switch (Ui) 816.sub.i outputs the pixel value D.sub.i from the input terminal INT of the parallel processor 8 to the register (Ri) 806.sub.i for holding only in a case where the write pointer signal WP is asserted.
The switch (Si) 818.sub.i writes the result of processing Q.sub.i from the arithmetic and logic unit (ALUi) 814.sub.i in the register (Ri) 806.sub.i only in a case where the write signal WW supplied from an address decoder 850 is asserted.
The switch (Vi) 826.sub.i reads the data held in the register (Ri) 806.sub.i and outputs the same to the output terminal OUTT of the parallel processor 8 only in a case where a write pointer signal WP is asserted.
The switch (Ti) 828.sub.i outputs the data held in the register (Ri) 806.sub.i to the read bit line RBi of the arithmetic and logic unit (ALUi) 814.sub.i only in a case where a read signal RW supplied from the address decoder 850 is asserted.
The individual delay element (Gi) 802.sub.i, individual delay element (Hi) 804.sub.i, register (Ri) 806.sub.i, switch (Ui) 816.sub.i, switch (Si) 818.sub.i, switch (Vi) 826.sub.i, and switch (Ti) 828.sub.i constitute the shift register (SR) 82.
The registers (Rij) 808.sub.i, 810.sub.i, and 812.sub.i hold the result Q.sub.i of processing of the arithmetic and logic unit (ALUi) 814.sub.i or the pixel value D.sub.i, which are supplied via the switches (Sij) 820.sub.i, 822.sub.i and 824.sub.i and the switch (Ui) 816.sub.i, respectively, and output the held data to the output terminal OUTT of the parallel processor 8 via the switches (Tij) 840.sub.i, 842.sub.i, and 844.sub.i and the switch (Vi) 826.sub.i. That is, the registers (Rij) 808.sub.i, 810.sub.i, and 812.sub.i operate as the registers which store the data in relation to the processing of the arithmetic and logic unit (ALUi) 814.sub.i, for example, the pixel values D.sub.i of the current frame and previous frame, an intermediate result of the processing, etc.
The switches (Sij) 820.sub.i, 822.sub.i, and 824.sub.i write the result Q.sub.i of processing of the arithmetic and logic unit (ALUi) 814.sub.i or pixel value D.sub.i in the registers (Rij) 808.sub.i, 810.sub.i, and 812.sub.i only in a case where the write signals WW0, WW1, and WW2 supplied from the address decoder 850 are asserted, respectively.
The switches (Tij) 840.sub.i, 842.sub.i, and 844.sub.i read the data held in the registers (Rij) 808.sub.i, 810.sub.i, and 812.sub.i only in a case where the write signals RW0, RW1, and RW2 supplied from the address decoder 850 are asserted, respectively, and output the same to the output terminal OUTT of the parallel processor 8 via the switch (Vi) 826.sub.i.
The registers (Rij) 808.sub.i, 810.sub.i, and 812.sub.i, switches (Sij) 820.sub.i, 822.sub.i, and 824.sub.i, and switches (Tij) 840.sub.i, 842.sub.i, and 844.sub.i constitute the register group 84.sub.i.
The arithmetic and logic unit (ALUi) 814.sub.i reads the pixel value D.sub.i or the data stored in the register group 84.sub.i etc. from the read bit line RBi, performs the processing, for example, an intra-frame movement detection processing, and outputs the result Q.sub.i of processing thereof or intermediate result to the register group 84.sub.i or the output terminal OUTT of the parallel processor 8 from the write bit line WBi.
Here, the read bit line RBi is the read bit line of the arithmetic and logic unit (ALUi) 814.sub.i, which arithmetic and logic unit (ALUi) 814.sub.i can read the data stored in the register (Ri) 806.sub.i and register group 84.sub.i by suitably controlling the switch (Ti) 828.sub.i and switches (Tij) 840.sub.i, 842.sub.i, and 844.sub.i via the address decoder 850.
Also, the output terminal OUTT is a write bit line of the arithmetic and logic unit (ALUi) 814.sub.i, which the arithmetic and logic unit (ALUi) 814.sub.i can write the data of the result of processing Q.sub.i, etc. in the register (Ri) 806.sub.i and register group 84.sub.i by suitably controlling the switch (Si) 818.sub.i and switches (Sij) 820.sub.i, 822.sub.i, and 824.sub.i via the address decoder 850.
Further, the arithmetic and logic unit (ALUi) 814.sub.i has data buses x.sub.i and Y.sub.i+1 for performing processing utilizing the data of the register groups 84.sub.i+1 and 84.sub.i-1 of adjoining individual processors 80.sub.i+1 and 80.sub.i-1, respectively.
The data bus X.sub.i is used for reading the data from the register group 84.sub.i+1 by the arithmetic and logic unit (ALUi) 814.sub.i, while the data bus Y.sub.i+1 used for reading the data from the register group 8.sub.i-1 by the arithmetic and logic unit (ALUi) 814.sub.i.
That is, the control circuit 852 controls the arithmetic and logic unit (ALUi+1) 814.sub.i+1 and makes the same read the data stored in the register group 84.sub.i+1 via the output terminal RBi+1 and to output the same from the arithmetic and logic unit (ALUi+1) 814.sub.i+1 to the arithmetic and logic unit (ALUi) 814.sub.i via the data bus X.sub.i.
Also, conversely, the control circuit 852 controls the arithmetic and logic unit (ALUi) 814.sub.i and makes the same read the data stored in the register group 84.sub.i via the output terminal RBi and to output the same from the arithmetic and logic unit (ALUi) 814.sub.i to the arithmetic and logic unit (ALUi) 814.sub.i+1 via the data bus Y.sub.i+1. Note that there is no arithmetic and logic unit (ALUi) 814.sub.i which should be connected to the data bus Y.sub.i, and therefore a numerical value 0 is input to the data bus Y.sub.1.
By these data buses X.sub.i and Y.sub.i+1, it is also possible for the arithmetic and logic unit (ALUi) 814.sub.i to perform processing by using the data stored in the register group 84.sub.i+1.
The control circuit (C) 852 produces an address signal ADRS and a control signal CTRL for controlling the arithmetic and logic units (ALUi) 814.sub.i and outputs the same to the arithmetic and logic units (ALUi) 814.sub.i and the address decoder 850.
The address decoder 850 decodes the address signal ADRS produced by the control circuit 852, produces the write signals WW, WW0, WW1, and WW2 and the read signals RW, RW0, RW1, and RW2, outputs the same to the registers (Ri) 806.sub.i and the register groups 84.sub.i, and controls these switches.
Below, the operation of the parallel processor 8 will be explained referring to FIG. 7. FIG. 7 is a view explaining the content of processing of the parallel processor.
As shown in the processing of [S11] in the horizontal period k, [T1], the pixel value D.sub.i of the video signal of the horizontal period k is serially input from the input terminal INTof the parallel processor 8. Simultaneously with the first pixel value D.sub.i being input to the input terminal INT, the read pointer signal RP is asserted and input to the input terminal RPT.
The asserted read pointer signal RP is given a delay at the individual delay elements (Gi) 802.sub.i whenever the pixel value D.sub.i is input to the input terminal INT and then is supplied to the switch (Vi) 826.sub.i.
The switch (Ui) 816.sub.i is closed when the read pointer signal RP supplied from the individual delay element (Gi) 802.sub.i-1 is asserted and writes the pixel value D.sub.i in the corresponding register (Ri) 806.sub.i. Accordingly, as shown in the processing of [S11], at the time of the ending of the horizontal period k, the pixel value D.sub.i of the horizontal period k is stored in all of the registers (Ri) 806.sub.i. The shift register (SR) 82 as a whole stores one line's (1H) worth of the pixel value D.sub.1.
Next, as shown in the processing of [S12] in the horizontal blanking period k shown in [T2], the control circuit 852 generates a predetermined address signal ADRS, asserts the read signal RW and write signal WW0 at the address decoder 850, and controls the switches (Ti) 828.sub.i and (SiO) 820.sub.i to close them.
By the above operation, the reading and writing of the data with respect to the registers of the register group 84.sub.i of the arithmetic and logic unit (ALUi) 814.sub.i become possible.
Next, in the horizontal period k+1 shown in [T3], as shown in the processing of [S13] and [S14], the control circuit 852 produces a predetermined address signal ADRS, asserts the read signals RW0 to RW2 and the write signals WW0 to WW2 in the address decoder 850, makes the switches (Sij) 820.sub.i, 822.sub.i, and 824.sub.i and switches (Tij) 840.sub.i, 842.sub.i, and 844.sub.i close, and enables the reading and writing of the registers (Rij) 808.sub.i, 810.sub.i, and 812.sub.i by the arithmetic and logic unit (ALUi) 814.sub.i.
Also, as shown in the processing of [S13], also in the horizontal period k+1, similar to the horizontal period k, the control circuit 852 stores the pixel value D.sub.i of the horizontal period k+1 input from the input terminal INT in the register (Ri) 806.sub.i. Simultaneously, as in the processing of [S14], the control circuit 852 controls the arithmetic and logic unit (ALUi) 814.sub.i, performs processing by using the data stored in the registers (Rij) 808.sub.i, 810.sub.i, and 812.sub.i, and returns the result of processing Q.sub.i thereof to (Rij) 810.sub.i.
Next, in the horizontal blanking period k+1 in [T4], as in the processing of [S15], the control circuit 852 produces a predetermined address signal ADRS, asserts the read signal RW1 and write signal WWin the address decoder 850, and makes the switches (Tij) 842.sub.i and switch (Ti) 828.sub.i close. Subsequently, the control circuit 852 controls the arithmetic and logic unit (ALUi) 814 and makes it record the result of processing Q.sub.1 stored in (Ril) 810i in the register (Ri) 806i via the read bit line RBi, arithmetic and logic unit (ALUi) 814.sub.i, and the write bit line WBi.
Next, in the horizontal period k+2 in [TS], as shown in the processing of [S16] to [S18], similar to the horizontal period k, the read pointer signal RP is asserted in the input terminal RPT, it sequentially is given a delay by the individual delay elements (Gi) 802i, and the resultant data is output to the switch (Vi) 826i. The switch (Vi) 826i sequentially outputs the result of processing Qi stored in the register (Ri) 806i to the output terminal OUTT of the parallel processor 8. Accordingly, one line's worth of the result of processing Qi of the individual processor 80i is sequentially output serially from the output terminal OUTT with the same data rate as that for the pixel value Di.
Further, as shown in the processing of the horizontal blanking period k+2 to horizontal blanking period k+3 shown in [T6] to [TS], in the horizontal periods k+1, k+2, . . . , also for the pixel value Di input to the parallel processor 8, the above-mentioned process lugs are carried out in the parallel processor 8, and the results of processing Qi thereof are sequentially output from the output terminal OUTT.
Note that, the operation of the parallel processor 8 is common with the second operation of the processing for the pixel value Di of a video signal of the HDTV system of the parallel processor 1 of the present invention which will be mentioned later by referring to FIG. 7.
In the above explained parallel processor 8, it is sufficient if each there is one address decoder 850 and control circuit 852 each with respect to all individual processors 80.sub.i. Namely, the parallel processor 8 is a parallel processor of an SIMD (single instruction multiple data) system having the same number of processor elements (individual processors 80.sub.i) as the number m of pixels of one horizontal period, that is, one frame period (1H).
In the processing of a video signal, usually identical processing is carried out with respect to all pixel values Di, and therefore the processing can be carried out without problem by the SIMD system. Also, it is sufficient if the parallel processor 8 of the SIMD system be provided with the address decoder 850 and control circuit 852 in common for the individual processors 80i, and therefore there is the advantage that the circuit scale becomes small.
While the number of pixels of one horizontal period of a video signal according to conventional systems, for example, the NTSC, is about 1,000, the number of pixels of one horizontal period of a video signal of the HDTV system is about 2,000. The SVP processing apparatus is configured so as to process one horizontal period's worth of pixel values in one horizontal period, and therefore the number of the individual processors 80i of the SVP processing apparatus must also be 2,000.
According to the current techniques for production of semiconductor devices, it is possible to make the number of the individual processors 80i of the SVP processing apparatus about 2,000. However, in a parallel processor 8, frequently both a video signal according to the conventional system and a video signal according to the latest system are subjected to the processing. Accordingly, there is a problem in that waste occurs in the circuit.
More specifically, where a video signal of the HDTV system is processed by using an SVP processing apparatus constituted by providing 2,000 individual processors so that a video signal of the HDTV system can also be processed, all individual processors will be used for the processing and therefore no waste will occur. Conversely, where processing of a video signal of the NTSC system is carried out by the same apparatus, 1,000 individual processors 80.sub.i will not be used, and there is then the problem such that waste will occur.
That is, where types of signals of data comprised of different lengths which serve as the unit of processing are handled in an SVP processing apparatus, it is necessary to provide a number of processors 80i corresponding to the type of data of the longest length. Such an SVP processing apparatus has a problem that it becomes over powerful with respect to a signal comprised of data of a shorter length than this.